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Switch Silicon

Open up any AI switch and the box is mostly sheet metal, fans, and optics. The part that actually decides how your fabric behaves is one chip in the middle of the board: the packet-forwarding ASIC. Two switches from two vendors can look identical on the data sheet — same port count, same 800G optics — and behave completely differently under an incast burst, because they're built on different silicon.

Almost nobody designs their own forwarding ASIC. The industry runs on merchant silicon — chips you buy from Broadcom, NVIDIA, Cisco, or Marvell and wrap in your own box. That's why "which switch vendor" and "which silicon" are partly separate questions, and why understanding the chips matters more than understanding the badges on the front panel.

After this page, you'll be able to
  1. Name the merchant ASICs that show up in AI switches and the bandwidth class each one ships in.
  2. Explain the shallow-buffer vs deep-buffer divide — why Tomahawk and Jericho are built for different jobs even at the same line rate.
  3. Separate the vendor choice from the silicon choice — why an Arista, a Cisco, and a white-box can all be the same chip underneath.
  4. Tie a silicon choice to a fabric strategy — scale-out Clos vs scale-across deep-buffer, and what each demands of your congestion control.

The merchant ASICs​

These are the chips you'll actually meet when you spec an AI fabric. Bandwidth here is the switching capacity of the ASIC — the total it can move across all ports at once.

SiliconVendorBandwidthBuffer modelRole in an AI fabric
Tomahawk 4 / 5 / 6Broadcom25.6 / 51.2 / 102.4 Tb/sShallow on-chip bufferHigh-radix, low-latency leaf/spine scale-out — the default for Clos AI fabrics.
Jericho3-AI / Qumran3 (+ Ramon fabric)Broadcom51.2 Tb/s class, paired with HBMDeep buffer + VOQ + scheduled / cell-based fabricScale-across — absorbs incast, lossless without leaning on PFC; used for the largest fabrics.
Spectrum-4NVIDIA51.2 Tb/s (64× 800G)On-chipThe silicon under Spectrum-X; adaptive routing in hardware.
Silicon One (G200)Cisco51.2 Tb/sDeeper bufferUnified routing + switching; powers the Cisco 8000, used by hyperscalers.
Teralynx 10Marvell51.2 Tb/sOn-chipMerchant alternative in the same shallow-buffer, high-radix class.

Notice that most of these land at the same 51.2 Tb/s generation. Line rate is not what separates them. The buffer model is.

The divide that defines the fabric​

Shallow versus deep buffer under incast, three senders converging on one egress port. Left, shallow buffer (Tomahawk-class): a small on-chip buffer of tens of MB fills in microseconds, so the switch must fire PFC and ECN to stay lossless — lowest latency and cost, but tuning-sensitive. Right, deep buffer plus VOQ (Jericho-class): a large HBM buffer of GBs with per-destination virtual output queues and a scheduled cell fabric absorbs the incast burst, staying lossless without leaning on PFC, at more cost and slightly more latency.
Same incast, two silicon answers — buffer it in HBM and schedule the fabric, or keep the buffer small and fast and engineer losslessness with PFC/ECN. This is the core AI-fabric silicon decision.

This is the one decision that shapes everything downstream, so slow down here.

Every forwarding ASIC has to answer the same question: when more traffic arrives for a port than the port can drain, where does the extra go? There are two schools of thought, and they produce two genuinely different kinds of chip.

Shallow-buffer (Tomahawk, Spectrum-4, Teralynx)​

The buffer is small, it's on-chip SRAM, and it's shared cleverly across ports. The bet is that you keep the chip cheap, the latency low, and the radix high — and you stop congestion before the buffer fills, using PFC and ECN out at the edges instead of soaking it up in silicon.

What you get:

  • Lowest latency — packets aren't sitting in a deep queue.
  • High radix — more ports per chip, which is exactly what a Clos spine wants.
  • Cheapest cost per port — on-chip SRAM is far cheaper than bolting on external memory.

What it costs you:

  • The buffer is tiny, so a few microseconds of incast can overrun it.
  • You stay lossless only if your PFC / ECN / DCQCN tuning is right.
  • Get the tuning wrong and you either drop (killing collectives) or spread PFC pause storms across the fabric.

This is the scale-out silicon — the chip you stamp out across leaf and spine in a Clos and lean on careful congestion control to keep lossless.

Deep-buffer + VOQ / scheduled fabric (Jericho, Silicon One)​

The opposite bet. Pair the chip with HBM so it has gigabytes of buffer, give every output port a virtual output queue (VOQ) so head-of-line blocking disappears, and run a scheduled, cell-based fabric: packets get chopped into fixed-size cells, sprayed across all internal paths, and reassembled at egress.

What you get:

  • Absorbs incast in HBM — a many-to-one burst that would overrun a shallow chip just gets buffered.
  • Lossless without leaning on PFC — the fabric grants before it sends, so it doesn't need pause frames to avoid drops. This is the same credit-before-you-send idea behind InfiniBand credit flow, built into the switch fabric instead of the link layer.
  • No hash polarization — cell-spraying uses every path evenly instead of pinning a flow to one link.

What it costs you:

  • More latency per hop — there's a scheduling round-trip the shallow chip skips.
  • More expensive — HBM and a scheduled fabric aren't free.
  • Lower radix and a heavier system (the Ramon fabric chips, the DDC chassis).

This is the scale-across silicon — the chip you reach for on the largest fabrics, where absorbing incast in hardware beats trying to tune your way out of it.

The takeaway​

Shallow-buffer is cheap, fast, high-radix, and tuning-dependent. Deep-buffer is expensive, lossless-by-design, and incast-proof.

Neither is "better." A Tomahawk spine and a Jericho fabric are answers to different questions. Most AI fabrics are Tomahawk Clos with disciplined congestion control; the biggest and the most loss-allergic reach for Jericho or Silicon One. How that buffer behavior plays out in practice — the actual knobs — is the whole subject of DCQCN, Buffer Profiles & Tuning.

Who builds on what​

Here's the part that trips people up: the badge on the front of the switch usually doesn't tell you the silicon inside.

Arista, Cisco, Juniper, and essentially every white-box vendor ship Broadcom silicon in most of their AI boxes. An Arista leaf, a Juniper leaf, and a no-name white-box leaf can all be the same Tomahawk underneath — what differs is the NOS, the support contract, and the automation story, not the forwarding behavior.

NVIDIA is the one vertically-integrated player — it builds its own Spectrum silicon and sells the whole stack (chip, switch, NIC) as Spectrum-X. Cisco is a hybrid: it ships Broadcom in plenty of boxes and its own Silicon One in the Cisco 8000.

So "which switch vendor" and "which silicon" are partly independent choices. When you compare two AI switches, the first question isn't the brand — it's which ASIC, and is it shallow or deep? The box that wraps the chip — the NOS, the optics, the support — is the subject of Switches for AI.

💡 What you should remember​

🧩Merchant silicon runs the fabricBroadcom, NVIDIA, Cisco, and Marvell build the ASICs; everyone else wraps them in a box.
⚡Line rate doesn't separate the chipsMost land at 51.2 Tb/s — the buffer model is what actually distinguishes them.
🪣Shallow = scale-outTomahawk: cheap, lowest latency, high radix — lossless only if PFC / ECN / DCQCN tuning is right.
🌊Deep + VOQ = scale-acrossJericho / Silicon One: HBM, virtual output queues, cell-sprayed scheduled fabric — absorbs incast, lossless without leaning on PFC.
🏷️Vendor and silicon are separate choicesMost boxes are Broadcom inside regardless of badge; NVIDIA is the one vertically-integrated stack.

Next: NICs & DPUs → — the silicon on the other end of the wire: where RDMA, congestion control, and packet spraying actually get offloaded.